News Analysis
Mentor taps NXP for design-for-test technology
By Richard Goering
05/07/08
Mentor Graphics has acquired rights to NXP Semiconductors' internal design for test (DFT) technology and tools, and has hired NXP DFT developers to staff a new R&D center in Germany. The deal gives Mentor new technology in automatic test pattern generation (ATPG) and yield learning.
Read more...
Contributed Article
How floorplanning guides synthesis and physical design
By Jack Erickson, Cadence Design Systems
05/06/08
Cadence Design Systems' Jack Erickson shows how to use floorplanning before synthesis with physical layout estimation (PLE), and before layout with silicon virtual prototyping (SVP). He discusses the floorplan information needed at each step.
Read more...
In My Opinion
Methodology standard will boost verification productivity
By Karen Bartleson
05/06/08
By defining a unified methodology for verification intellectual property (VIP) interoperability, Accellera's new VIP technical subcommittee can boost verification productivity, says Synopsys' Karen Bartleson. It can also head off a potential standards dispute between different SystemVerilog methodologies.
Read more...
First Look
Startup targets next-generation physical verification tools
By Richard Goering
05/06/08
Startup Polyteda Software Corp. is developing physical verification software that will be able to handle complex ICs 10 or 15 years into the future, according to founder Vlad Marchuk, president and CEO. The company is making its first public appearance at the Design Automation Conference in June.
Read more...
Feature Story
FPGA design requires low-power techniques
By Tets Maniwa
05/06/08
Power is becoming a major design consideration for FPGAs. In this article we review why FPGA power consumption is increasing, and discuss various techniques that can be used to reduce it.
Read more...
News Analysis
New exhibitors bring fresh ideas to DAC
By Richard Goering
05/05/08
With some two dozen first-time exhibitors in 2008, the Design Automation Conference continues to provide a showcase for new solutions for system and chip design. We profile some of the EDA and silicon IP providers who are making their first appearance at the 45th annual DAC in June.
Read more...
First Look
Transient noise analysis tackles tough analog circuits
By Richard Goering
05/01/08
Claiming to make transient noise analysis practical for complex analog circuits such as ADCs and PLLs, Berkeley Design Automation has released a Noise Analysis Option for its Analog FastSpice simulator. The option analyzes random device noise and claims true Spice accuracy.
Read more...
First Look
Cadence offers new custom IC design capabilities
By Richard Goering
04/29/08
In a broad-ranging upgrade to its Virtuoso custom IC design platform, Cadence Design Systems is promising tighter manufacturing integration, improved parasitic analysis, high-performance parameterized cells (p-cells), space-based routing, and faster analog circuit simulation with multicore support.
Read more...
In My Opinion
Defining an infrastructure for virtual platform design
By Michel Genard, Virtutech
04/29/08
Virtualization greatly accelerates system-on-chip and software development, but an underlying infrastructure is needed, says Virtutech's Michel Genard. He reviews several standards efforts that can help.
Read more...
Contributed Article
Open Verification Methodology allows reusable testbenches
By Mike Baird, Willamette HDL
04/29/08
The Open Verification Methodology (OVM) provides a methodology for writing advanced testbenches, says Mike Baird, founder of training firm Willamette HDL. He reviews a number of techniques for building reusable testbenches.
Read more...
First Look
Startup automates clock gating and power measurement
By Richard Goering
04/28/08
Startup Envis can automate IC power reduction techniques that would take weeks or months to do by hand, says Paul McLellan, CEO. Envis this week (April 28) is rolling out tools for power estimation and clock gating.
Read more...
News Analysis
New standards effort targets verification IP interoperability
By Richard Goering
04/28/08
The Accellera standards organization has launched a verification IP (VIP) technical subcommittee that will seek to define a standard methodology to allow VIP interoperability and reuse, SCDsource has learned. The effort could head off a potential standards dispute involving Cadence Design Systems, Mentor Graphics and Synopsys.
Read more...
First Look
Startup offers open source FPGA floating-point library
By Richard Goering
04/25/08
Alan Coppola, president of silicon IP startup OptNgn Software, is launching his company by giving something away – an open-source floating-point VHDL library for FPGA designers. It's the first step in a plan that will lead to commercial IP libraries and a parallelizing compiler.
Read more...
In My Opinion
Don't compromise on true Spice accuracy
By Paul Estrada, Berkeley Design Automation
04/23/08
Digital fast Spice may be accurate to within 1 percent of Spice simulation, but that isn't good enough, says Paul Estrada, COO of Berkeley Design Automation. That 1 percent, he says, can make the difference between successful silicon and a respin.
Read more...
Contributed Article
Using formal verification for post-silicon debug
By Lawrence Loh and Jay Littlefield, Jasper Design Automation
04/23/08
Formal property checking can greatly speed post-silicon debug, according to Lawrence Loh (shown) and Jay Littlefield of Jasper Design Automation. They show why a formal approach can help and how it should be used.
Read more...
First Look
ChipVision offers ESL synthesis for low-power ICs
By Richard Goering
04/22/08
ChipVision Design Systems is moving from electronic system level (ESL) power analysis to design implementation by rolling out PowerOpt, a SystemC synthesis tool that generates RTL for low-power ICs. Another new offering, P-SAM, provides a power model development service for virtual platforms.
Read more...
Conference Coverage
Speaker: Let's get 'manycore' parallel programming right
By Richard Goering
04/18/08
To develop parallel software for "manycore" systems-on-chip (SoCs), we need to stop repeating the mistakes of the past, said Tim Mattson, parallel computing evangelist at Intel. At the Electronic Design Processes (EDP) workshop April 17, Mattson presented rules that will help avoid those mistakes.
Read more...
Conference Coverage
Case study reveals challenges of multicore programming
By Richard Goering
04/18/08
CLK Design Automation's Amber is a multi-threaded static timing analyzer that runs on multicore platforms. A presentation by chief architect Joao Geada at the Electronic Design Processes (EDP) workshop revealed some of the challenges such applications pose.
Read more...
Conference Coverage
Keynote: System-level approaches scale the power wall
By Tets Maniwa
04/18/08
The greatest power reductions come from system-level approaches, said Jan Rabaey, professor of electrical engineering and computer science at the University of California at Berkeley, at the OpenAccess Conference April 16. Rabaey discussed "always-optimal" systems and "aggressive deployment" tactics.
Read more...
Conference Coverage
'Green Tech' panelists: System design curbs energy waste
By Richard Goering
04/16/08
Embedded system designers can play a key role in reducing energy consumption, said speakers on a "Green Tech" panel at the Embedded Systems Conference April 16. But panelists noted that the entire system must be optimized, including processors, memory, storage, and software.
Read more...
Contributed Article
Validating false path timing exceptions
By Ashish Batra, Girish Patil and Angela Kristic, Cadence Design Systems
04/15/08
It's crucial to validate false path timing exception constraints, say authors from Cadence Design Systems. They describe types of false paths, present sensitization approaches, and show that a path that appears "false" might actually be "true" in silicon.
Read more...
First Look
Synplicity initiative eases IP evaluation for FPGAs
By Richard Goering
04/15/08
Using encryption technology now undergoing IEEE standardization, Synplicity is launching its ReadyIP initiative, which lets FPGA designers evaluate third-party IP before licensing it. Initial IP vendor partners include ARM, Cast, Gaisler Research, and Tensilica.
Read more...
In My Opinion
It's time to shift the low power debate
By Steven E. Schulz, Si2
04/15/08
It's time to move beyond disputes over low-power specification formats, and tackle much larger problems with power modeling, system-level design, and power optimization, says Steven Schulz, president of the Silicon Integration Initiative (Si2).
Read more...
News Analysis
Pyxis, Silicon Canvas claim interoperability breakthrough
By Richard Goering
04/11/08
Can IC designers select best-of-breed tools and still have the tight integration provided by single-vendor solutions? A demo at the April 16 OpenAccess Conference, where Pyxis and Silicon Canvas will run their respective tools using a shared memory run-time model, suggests so.
Read more...
To find more articles in this category please make sure to set the date filter to a broader range in the menu on the left.
