First Look
Silicon Frontline Aims at Post-Layout Verification
By Editorial Staff
06/23/09
Silicon Frontline Technologies has announced two products aimed at post-layout verification. Both tools incorporate a patent-pending 3D technology that claims to deliver a “guaranteed accurate” solution for full-chip 3D parasitic extraction with performance equivalent to 2D tools. SCDsource digs deeper.
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Validating Advanced Foundry Models
By Steven Zhang and Tim K. Smith
06/04/09
How can an engineer analyze foundry models to understand their behavior, limitations and robustness? The authors describe a comprehensive and automated methodology for evaluating foundry models and analyzing a design’s performance, including layout effects.
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Post CommentSpecial Technology Report
Mixing Formal and Dynamic Verification, Part 2
By Bill Murray
05/29/09
In this second part of our report, we discuss the detailed survey results, see how formal is being used with dynamic verification, look at the application of formal in the ESL space, and hear from technology users and technology providers how formal methods might look in 2012. Plus see our formal cartoon!
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Our Exhaustive Proof Cartoon
By Max Lorenz
05/06/09
Do you have to be a mathematical genius to use formal verification methods? Our artist in residence poses the question.
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Letter from the Publisher
Driving Growth in 2009: What Will it Take?
By Francine Bacchini, Tech Source...
06/29/09
Recently, SCDsource explored possible article ideas with a group of engineering directors and VPs, all concerned with the issue of shrinking design budgets and engineering resources. Questions arose about what they were doing, or doing differently, to ensure that their products got out the door and into the hands of their customers. Here is what they had to say, as well as an invitation to share your thoughts on ways to spur electronic industry health and wellness.
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Using IP standards to speed path to executable specifications
By David Murray and Zoltan Sugar
06/23/09
The authors describe the formalization of IP metadata to facilitate IP-centric design reuse and automation, using IP-XACT as a formal data interchange mechanism. They also show a case study of an end-to-end flow from informal metadata to fully automated SystemVerilog generation.
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High-density QAM chip targets “any content, anytime” cable services
By Bill Murray
06/15/09
BroadLogic claims that its new TeraQAM chip enables the delivery of personalized services by pushing the network edge closer to the consumer. The new chip quadruples QAM density per port while reducing system cost by up to 80 percent and power consumption by 85 percent.
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SCDsource Expands Scope
By Francine Bacchini, Tech Source...
05/06/09
While SCDsource will continue to cover EDA, the publication is evolving to encompass the news and information needs of the overall electronics supply chain. Beginning this month, SCDsource will be publishing expanded editorial content, contributed “how to” articles, viewpoints and other vital technical news and information that can help decision-makers up and down the electronics supply chain make better informed decisions.
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First Look
Mentor Catapult C synthesizes control and power management
By Bill Murray
06/30/09
Mentor has enhanced its Catapult C high level synthesis tool with the ability to synthesize control logic and power management functionality. It has also announced a patent-pending automated verification flow that enables easy debug of the RTL against C.
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Accellera and SPIRIT to merge
By SCDsource
06/30/09
The merged entity – dubbed Accellera – will improve the development of language-based and IP standards. Accellera is the leading standards organization developing language-based standards used by system, semiconductor, intellectual property (IP) and EDA companies. The SPIRIT Consortium is the leading standards organization focused on developing standards for IP deployment and reuse. Further details will be announced at the Design Automation Conference (DAC) in San Francisco, the week of July 27, 2009.
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Learn moreNews Bytes
Wi2Wi announces new GPS module with 30% lower power consumption. The module utilizes the CSR/SiRF Technologies™ SiRFStar III LPx™ architecture designed specifically for embedded products such as personal navigation devices, mobile internet devices (MID), ultra-mobile PCs (UMPC), ruggedized PCs, automotive aftermarket GPS systems and multifarious medical, industrial, and defense systems that feature GPS capability.
Microchip announces industrial / scientific / medical (ISM) band, sub-GHz transceiver radio for bi-directional, short-range wireless applications. The MRF49XA covers the 434/868/915 MHz unlicensed ISM band, which is ideal for low data-rate, low-power embedded wireless applications.
