Print
Expert's Corner
Design for manufacturability gears up for 32 nm
By Richard Goering
04/22/08
Design for manufacturing (DFM) has become part of the mainstream IC design flow, but many tough problems remain to be solved, according to DFM luminary Andrew Kahng. A longtime researcher in the field, Kahng is professor of computer science and engineering and of electrical and computer engineering at the University of California at San Diego (UCSD). He is also co-founder of startup Blaze DFM. In this Q&A interview, Kahng talks about what's in use today, what's needed for 32 nm, the role of restricted design rules, the importance of electrical DFM, and directions for future research.SCDsource: People have been talking about DFM for years. How successful is it today?
Kahng: DFM is quite successful today. I think we can say that techniques such as DRC [design rule checking] and RET [resolution enhancement technology] are now mainstream. CAA [critical area analysis] and optimization is also fairly standard, and so is CMP [chemical mechanical polishing] modeling, as well as lithography hotspot detection and minimization. Newer electrical DFM techniques to maximize parametric yields are not as pervasive, but are being actively developed and deployed.
While we can say that the above list represents success, clearly DFM is not as pervasively deployed as is needed by the industry. Deployment takes time due to complex foundry-design dependencies. And there is a traditional mindset that EDA tools for DFM are kind of a last resort for variability mitigation. Manufacturing variability is under attack from many directions -- equipment makers, metrology tools, automated process control methodologies, process engineers, OPC [optical proximity correction] engineers, the conservative modeling team, the conservative design rule manual, clever circuit and layout designers, and yield engineers -- and then EDA gets its shot. The industry has needed time to reach consensus that those other variability mitigations aren’t enough, and that DFM tools have measurable value.
SCDsource: What is your definition of DFM?
The first precept means that manufacturing must truly comprehend slacks and sensitivities, criticalities, and chip-level design objectives such as timing and power, and reliability and yield. The second means that systematic variations must be fully comprehended in the design flow. We must learn how to pull whatever we can out of the random variability bucket, and move it into the systematic variability bucket. Pulling out the systematic variations enables us to deal effectively with the actual random variations and find more value in statistical signoff and design methods.
The third precept tells us not to change the handoff or the flow – it’s too big a war to fight, it’s often unnecessary, and the time constants are too long.
SCDsource: At the recent Electronic Design Processes workshop (EDP 2008), Blaze co-founder Puneet Gupta talked about "manufacturing aware design" (MAD) and "design aware manufacturing" (DAM). Can you give an example of each?
Kahng: For MAD, a good example is CMP model-aware fill and timing/signal integrity optimization. For DAM, I’d like to say that my research group is really hot on what we call "Design for Equipment" – or, perhaps more properly, "Design to Equipment." A few years ago, we developed placement methods that took into account a lens aberration map to improve timing yield. At the Design Automation Conference (DAC 2008) this June, we will present a flow that transforms design intent in terms of timing slack into simultaneous frequency improvement and leakage savings by telling the step-and-scan tool how to modulate the exposure dose across the reticle field. ASML tools have a DoseMapper capability that modulates the exposure dose for improved process control. We can leverage this capability to achieve frequency gains and leakage reductions.
SCDsource: What additional DFM tools will be needed at 32 nm and below?
SCDsource: What tools and methodologies are used in the pre-GDSII design flow today?
Kahng: The list on the tools side includes CAA analysis and optimization, supported by foundry kits; via doubling; CMP modeling, fill-pattern optimization, and post-CMP topography-aware extraction supported by foundry kits; lithography hot spot detection and minimization supported by foundry kits; and timing-driven fill and IR drop-reducing and dynamic power-reducing fill.
On the methodology side, some examples are statistical signoff; restricted layout styles such as single-orientation gate poly and restricted pitches; library cell methodologies to decrease variability and improve composability in the placement and routing block, an example being dummy poly; more proactive pattern density management on all layers, including active and via layers; coarse-grain gate-length biasing built into cell libraries; and some connecting of dots such as spread-fatten-fill and RET-aware routing and fill.
SCDsource: What DFM methodologies will designers use as we move to 32 nm and 22 nm?
Kahng: Without question, there must be increased use of restricted design rules (RDRs). Big fabless consumer companies have made it the foundry’s problem to achieve high yields while imposing only minor layout restrictions. But "minor" actually means more design rules and special-casing – and a waste of the router’s attention. I think people are belatedly realizing this.
More important, the reduction of variability that comes with radical restrictions such as discrete pitch or single orientation may very well outweigh any perceived area increase with restricted layout. This is because tighter guardbands lead to less consumption of area and power in the synthesis, placement and routing outcome, not to mention faster design closure and turnaround time. We recently published a paper at ISQED 2008 suggesting a reduced guardband design methodology whereby the designer can artificially tweak model guardbands in the flow to get smaller die with less design effort, and achieve an overall win of good die per wafer. The point is that RDRs may be much less costly than people think today. The other key point is that RDRs will be required anyway – even at 32nm, I don’t see how the variability associated with double-patterning due to overlay and pattern split will be compatible with unrestricted layout.
In my view, some of the consensus target technologies that the industry focuses on are actually lower-order bits, solving self-inflicted problems. One example is the emphasis on lithography-simulation based electrical analysis, which is basically a consequence of putting off the transition to RDRs. Often, problems are attacked at only a late stage in the flow, whereas it would be much more cost-effective to attack them upstream. For example, we still find and fix critical-layer hotspots post-layout. It is better to find and fix them in detailed placement.
A lot of area, power and yield is left on the table in chip implementation – but the industry is curiously slow in coming up with manufacturing-aware solutions. For example, the goal of variation robustness along the lines of the self-compensating design paper we published in DAC 2005 seems like a no-brainer. Right after the model, predict, and compensate mantra, the next line of defense against variability has to be variation robustness.
SCDsource: What additional DFM tools will be needed at 32 nm and below?
Kahng: If I had to guess what will be available to designers for the 32 nm node, I would say we will see more lithography simulation-based electrical analysis, lithography simulation-based standard cell characterization, statistical timing and statistical leakage analysis, finer gate-length biasing, and stress-aware design optimization. For the last point, we’re starting to hear about prototype methodologies that are along the lines of what we published at ICCAD 2007, which noted that there is a lot left on the table if you guardband the pattern dependencies of stress and strain.
I hope the industry can learn from the costly experience of ignoring stress until so late – modeling, analysis, and optimization needs were very clear but no one did anything about it. We have a similar situation coming up with double-patterning and what can be termed the "bimodal challenge," in which neighboring gates are printed with different exposures, and are therefore drawn from two distinct statistical distributions, resulting in an overall bimodal distribution. I’ve discussed some of the modeling, analysis, and design optimization challenges in a plenary talk at SPIE Advanced Lithography, and more recently at ISPD [International Symposium on Physical Design]. I believe it will be very costly to the industry if we don’t update the modeling infrastructure and tool flows in time.
Next PageBack to Expert's Corner