A reference flow consisting of “best practices” for power-aware IC design was recently developed within the Low Power Coalition (LPC) of the Silicon Integration Initiative (Si2). Rather than focusing solely on the RTL-to-GDSII portion of the design cycle, the LPC developed a holistic, flow-centric approach to address the entire process. In particular, the flow raises the starting point to electronic system level (ESL) design, noting the opinion of experts that the impact on low power design is greater as one moves up in design abstraction.

 

Design for power is similar to performance and area optimization, and should be added as the third dimension of the design closure process. The power-aware design flow described here provides a generic flow template to address power closure in different system requirements and operating environments. As an example, the power aware flow can be easily adapted for energy optimization of a held-held mobile phone device or to reduce the thermo design power (TDP) of a desktop microprocessor.

 

It is logical to separate the power aware design flow into three phases based upon design abstraction levels. Such a separation provides a framework to better understand the tradeoffs between accuracy and tool performance within the flow. The power aware flow presented in this article starts at the architecture/system design phase, and includes design steps right until the chip finishing stage (Figure 1).

 

 

 

The ESL phase of the design process includes the evaluation and verification of a high-level system (product) specification to arrive at a suitable system architecture (Figure 2). It produces design constraints and intent that may be used in downstream design steps at the RTL and lower levels.

 

This phase provides a platform for system and block level power, performance, and area tradeoff analysis and optimization. It includes the selection of large IP components and the selection of the target process. Firmware and hardware algorithm partitioning is also done at this level, as is the creation of power and energy budgets for subsequent design phases. High level power analysis enables algorithmic and architectural tradeoffs as well as verification of basic power goals and budgets.

 

 

 

The high level of abstraction in the ESL phase enables power simulation with real world applications for system-on-chip (SoC) design. Optimization in this phase provides the most gain in terms of power reduction, but lacks micro-architectural details.  Limited high level power models and missing physical information can result in limited power analysis accuracy in the ESL phase. Since dynamic power can often map to signal switching activities, profiling switching activity by application can help reduce system level active and standby power.

 

Accuracy issues at the ESL phase could very well curtail the effectiveness of fine-grained optimizations. But, with the ability to execute real world applications and predict the right power trends, an ESL power analysis flow can enable decision making for system-level issues. These may include the number of power modes to use, the types of power management policies to be implemented, and the type of hardware support needed for various power management algorithms.

 

The design phase encompasses the detailed selection, modification, coding and interconnection of RTL descriptions of the major subsystems within the selected architecture (Figure 3). Each sub-system is mapped into one or more power domains, and the modes of operation for the design are refined into specific nominal operating conditions for each domain.

 

Domains that must preserve state (or some portion thereof) are identified. Rules for the treatment of inter-domain signals are defined. RTL power analysis and linting is performed with static and dynamic power targets for each power mode. The power modes are decomposed into dynamic and static power budgets and constraints for each power domain at its appropriate operating condition. These are used in the subsequent implementation phase.

 

 

 

RTL power analysis is more accurate than ESL because the micro-architecture of the design is well defined and is fully coded in RTL. Tools are available using quick logic mapping for power analysis, but accuracy may still be lacking as compared to the implementation phase because mapping RTL to gates may not exactly compare to final synthesis. Additionally, physical layout information is usually not available in this phase of the design. Nevertheless, the analysis accuracy is good enough to validate power budgets and to provide good guidance to enable low power micro-architecture selection and to support clock and datapath power optimization.

 

Since clock power usually accounts for 30% to 40% of total dynamic power, an important  power reduction technique that can be employed in the design phase is medium and fine grained clock gating. The design phase is also the place in the flow where logical partitions of the power domains are fully defined.  Common Power Format (CPF) and Unified Power Format (UPF) commands are used to verify the power intent of the design through simulation and verification.

 

The implementation phase involves the mapping of RTL and power constraints and budgets through synthesis and physical design and analysis into physical blocks and components that can realize the design intent (Figure 4). Implementation tools must ensure that all power constraints are satisfied. In particular, implementation tools may generate additional constraints that must be satisfied by subsequent tools in the design flow.

 

Since both detailed gate and physical information are available at this point, the power analysis in this phase should be the most accurate. The performance of a full chip analysis running real workloads, however, could limit the amount and type of analysis that can be done at this level. Performance and data related issues can be minimized by identifying limited worst cases stimulus for each area of the power analysis, and using these to drive the optimization techniques used in implementation phase power closure.

 

Power optimization techniques that can be used in the implementation phase include power grid planning strategies, clock tree optimization, leakage optimization with Vt and long channel devices, and reduction of parasitics on high activity nets.
 

 

Power closure is the task of implementing or modifying the design such that the power objectives, singular or plural, are met (Figure 5). At each stage of the design flow there are points at which power information can be analyzed to determine if the constraints have been met so they can be signed off or “closed.” Power closure can and should thus be accomplished during each phase of a power aware flow.

 

 

 

The power closure process is not necessarily unidirectional. To continually improve accuracy and reduce the margins, feedback from silicon measurement data and power analysis data from subsequent design phases can be used to fine-tune power models, operating conditions, and power stimulus.