Much of the news about semiconductor, systems and EDA providers in 2008 had to do with business and financial challenges. Even so, electronic design technology is moving ahead in a number of key areas. In this article we identify ten top emerging technology trends for 2009. Some are similar to the 2008 trends identified by SCDsource, while others are new, such as 3D ICs and electronic system level (ESL) design for low power.

 

1. Analog/mixed-signal design gains speed and automation
2. ESL goes mainstream with synthesis and virtual platforms
3. Low power design moves up to ESL
4. Silicon virtual prototypes move beyond floorplanning
5. Verification overcomes limits of constrained-random simulation
6. Ecosystem emerges for 32 nm and 22 nm design
7. 3D ICs gain interest and tool support
8. EDA software rides multicore wave
9. Interoperability efforts aid design and verification
10. FPGA design looks like ASIC design

Given this environment, 2009 may result in fewer than expected design starts, reduced semiconductor and EDA industry R&D, continuing shortfalls at publicly-held EDA companies, and less venture capital funding for startups. But people will still be designing complex chips and systems, and will be looking for tools and methodologies that can reduce costs with improved results or, at least, without sacrificing results. Those who can provide such technology should find ready buyers.

 

 

At a DesignCon panel in early 2008, Gary Smith, chief analyst at Gary Smith EDA, predicted that 2008 would be the “year of analog.” These were prophetic words. In 2008, Synopsys and Magma Design Automation both rolled out analog/mixed-signal design suites that compete with the venerable Virtuoso from Cadence Design Systems. There was also considerable activity in the Spice and Fast Spice simulation markets, with new tools promising Spice accuracy at much higher speeds.

 

The big question for 2009 is adoption. Analog designers have traditionally resisted change, but that resistance may be easing. At the DesignCon panel, Smith noted that veteran analog engineers who have been locked into using only Spice are nearing or at retirement, while many new engineers don't identify themselves as digital or analog engineers, but as electronics engineers. They have no bias towards any existing tools and methodologies, he said. Others have noted that the incremental value-add of new analog tools has historically not been sufficient to justify the cost of switching. New tools coming along may break that mold.

 

For instance, Cadence has long dominated analog IC design with Virtuoso and with parameterized cells (p-cells) written in Cadence’s Skill language, but the emergence of interoperable p-cells on the OpenAccess database is challenging that franchise. In 2008 Magma rolled out Titan, a "full chip" mixed-signal design, analysis, and verification platform. Titan can read both Skill p-cells and Python-based "PyCells" generated by software from Ciranova.

 

In September, Synopsys rolled out Galaxy Custom Designer, which claims to be the first analog/mixed-signal implementation tool built natively on OpenAccess. It supports both legacy designs and those based on interoperable process design kits (PDKs). Synopsys is one of a growing number of companies supporting the Interoperable PDK Libraries (IPL) initiative. Ciranova, meanwhile, introduced Helix, which uses PyCells and claims to automatically generate analog placements comparable in quality to handcrafted design.

 

“In 2009, efficient automation tools for creating reusable and portable analog IP will be available,” said K.T. Moore, senior director of Magma Design Automation’s custom design business unit. “Semiconductor companies will accelerate adoption of newer process technologies, enabling the creation of large analog IP libraries.”

 

Meanwhile, analog verification is pushing the envelope in both speed and accuracy. Nascentric's OmegaSim GX fast Spice simulator uses the nVidia Tesla C870 GPU, a PCI Express graphics card that includes 128 multi-threaded processors. Startup Gemini Design Automation announced a multi-threaded, Spice-accurate simulator that threads both the model evaluation and matrix solving components of the simulator. Startup Infinisim claims Spice accuracy with several orders of magnitude speedup, thanks to its “real-time adaptive simulation” approach.

 

2009 will sound the “death knell” for traditional FastMOS (fast Spice) products, predicts Kent Jaeger, vice president for sales and marketing at Gemini. “You will see the convergence of [fast] Spice simulation techniques embedded as options to true and traditional Spice accurate simulators,” he said. “Products which have only Spice-accurate or FastMOS techniques will likely go by the wayside.”

 

Analog verification is also moving to higher levels of abstraction. Verilog-AMS is proving useful for some designs, and a draft standard for SystemC analog/mixed-signal extensions was recently released. Bradley Geden, product marketing manager for Fast Spice at Synopsys, says 2009 will bring “advanced AMS verification methods that provide customers with the benefits of digital verification methodologies. Huge efforts are underway to define AMS extensions to SystemVerilog, as well as the analog equivalent of assertions.”

 

 

ESL design has been talked about for years. Growing interest in two aspects of ESL – high-level synthesis and virtual platforms – suggests that mainstream adoption is beginning. 2009 “will be the year of ESL adoption as design teams of all types begin implementing a viable, production-proven ESL flow,” predicted Brett Cline, vice president of marketing and sales at Forte Design Systems.

 

One sign of the times: in November, John Cooley ran a posting in the E-Mail Synopsys Users Group (ESNUG) newsletter detailing “the first US-based C/C++ chip design I’ve seen.” It used Mentor Graphics’ Catapult C compiler. No longer, it seems, is high-level synthesis use restricted to a few large Japanese consumer product companies.

 

Cadence moved into high-level synthesis in 2008 with its C-to-Silicon Compiler, which takes in SystemC or C/C++ code and generates Verilog RTL. Significantly, it claims to handle both datapath and control logic. Meanwhile, Forte and Calypto Design Systems announced a SystemC design flow including both implementation and verification, and Synfora improved its algorithmic synthesis technology to generate larger blocks.

 

Virtual platforms, or software virtual prototypes, were the subject of intense interest in 2008. As reported in SCDsource in early 2008, these tools are becoming increasingly important for embedded software development, which is increasingly more of a bottleneck than hardware design.

 

“As virtualized software development becomes increasingly mainstream, look for more standardization among virtual platforms so that engineers can tackle any assignment with the same development platform,” said Michel Genard, vice president of marketing for Virtutech.

 

Imperas brought a new idea to the market in March 2008 with Open Virtual Platforms (OVP). With APIs, models, and a simulator, OVP promises an open, standard infrastructure for virtual platform development. Other virtual platform providers, however, are embracing the Open SystemC Initiative (OSCI) transaction level modeling (TLM-2) standard, released in mid-2008, as the best path towards model interoperability between virtual platforms.

 

“Now that interoperability issues have been addressed with the introduction of SystemC TLM 2.0 APIs, virtual platforms for embedded software development are ready to enter mainstream adoption,” said Frank Schirrmeister, director of product marketing for system-level solutions at Synopsys.

 

TLM-2 brings interoperability to a range of ESL applications. According to Mike Meredith, OSCI president, TLM-2 provides “an ESL framework for architecture analysis, software development, software performance analysis, and hardware verification. After six months, we are seeing increased adoption and support of the standard by users as well as IP and tool vendors.”