This paper presents some of the key criteria for selecting and integrating high-speed mixed-signal connectivity intellectual property (IP) in 65 nm and 40/45 nm geometries. A selection criteria for third party IP will be proposed, followed by a discussion of the key steps needed to integrate third party mixed-signal IP successfully into a system-on-chip (SoC). Mixed-signal integration issues – such as noise and crosstalk – will also be addressed using PCI Express 2.0 and DDR2 as examples. In addition, the paper will address why a structured verification process is imperative at these deep sub-micron technologies in order to achieve yield and to ensure long time reliability.

 

The selection criteria can be categorized as functional correctness, integration and usability, and cost of ownership. Obviously, the IP must be correct functionally, but additional factors such as ease of integration and available support by experienced protocol experts are also important. Most companies have design teams located worldwide, so the IP vendor must be able to provide their support 24/7 in the local language.

 

Also, it is important to understand the cost that the IP can impose on a company in terms of maintenance, support and products that use the IP. A key element of reducing end user cost and risk is the availability of test-chip prototypes or FPGA demo boards to help the designer integrate their logic around the IP and validate it through emulation.

 

Functional correctness is achieved by a thorough verification methodology. For mixed-signal IP, pre-layout verification is becoming a poor predictor of performance. This increases the importance of post-layout parasitic extracted simulations due to the systematic variations based on physical changes to the device.

 

Variation due to device size is well understood, and Monte Carlo simulations can be extensively used to evaluate the impact of threshold voltage and saturated drain current mismatch. However, systematic variations based on physical changes to the device can occur during manufacturing, including shallow trench isolation (STI) stress, well proximity, optical proximity and phase shift effects (OPC/PSM), and hot carrier injection (HCI). Post-layout verification needs to consider all these factors. Also, at high speeds, there are additional factors to consider in the post-layout verification phase, such as package models that assume a worst-case or pessimistic environment, and primary and secondary ESD protections.

 

With high-speed serial interconnects manufactured in 65 nm and 40/45 nm technologies, test chips and silicon characterization are integral to the validation methodology. In order to ensure manufacturing robustness, test chips must be processed using split-matrix lots where critical parameters such as threshold voltage and mobility are varied.

 

Special testing equipment, including high-speed oscilloscopes, data generators, bit-error rate testers, and compliance test sets are traditionally used to verify the quality of the electrical signaling. These will measure the eye-diagram, jitter generation, jitter tolerance, and other electrical parameters necessary for serial link certification. The challenge is that bandwidths required to accurately measure the high-speed serial links may not be possible with today’s test equipment, or it becomes very expensive in terms of equipment cost, calibration and setup.

 

To address these concerns, new silicon validation methodologies provide direct visibility into the received eye of the high-speed serial interconnect, without using any special testing equipment to show the link performance. This allows the user to measure the actual eye at the receiver, and eliminates the need for expensive test equipment and hardware with SMA connectors to measure a link in the lab or in the field. In addition, the impact of transmitter pre-emphasis and receiver equalization can be evaluated, which provides additional information on link frequency when used in an asynchronous system. For validation at the system level and for board fault analysis, IEEE-1149.6 AC JTAG support is also included in this methodology.

 

IP deliverables include Verilog RTL, LEF for floor-planning, .lib for timing, GDSII layout files, a detailed foundry specific implementation reference book, and the Spice model of the I/O. For protocols such as PCI Express, these deliverables need to be dedicated to the particular lane configuration, for example x1, x4, x8 or x16. Starting with these deliverables, the SoC designer should follow the steps described below when integrating high speed mixed-signal connectivity IP:

After the running gate-level system simulations, physical design commences. One important consideration is IP spacing requirements – that is, determining which blocks can be put adjacent to the IP. Isolation techniques such as N-P-N (triple) guard-ring implementation and deep n-well isolation can be implemented.

 

The type of packaging is another consideration. Should it be flip chip or wire bond? This decision may be dictated by the IP at high speeds. Due to crosstalk, it may be preferable to consider a package with low parasitic inductance.

 

In addition to the type of package, there are many other factors that influence the overall noise and crosstalk performance. An example of these effects using DDR2 is provided below.

 

 

The benefits of high performance DDR2 SDRAM memories require SoC interface designers to approach memory subsystem integration with attention to detail. As data rates have increased from DDR2 400, DDR2 533, DDR2 667, and now DDR2 800, the complexities associated with the timing and signal integrity of the memory interface has increased significantly.

 

Total timing is composed of three budgets: transmitter, interconnect and receiver. Nominally, each of these three budgets account for about 33% of the total timing budget. JEDEC managed to scale down the DRAM contributors to the transmitter budget during reads, in addition to the receiver.

 

In Figure 1, the individual losses are color coded.

 

Orange: During write, timing must account for SDRAM set up and hold. This is 100 ps for setup from the AC threshold and 175 ps for hold to the DC threshold, corresponding to 225 ps setup and hold. Remaining budget is 525 ps for both setup and hold.

 

Green: Routing skews in package and PCB remove 35 ps. Remaining budget is 490 ps for both setup and hold.

Purple: Tx contributions from controller remove an additional 175 ps from the budgets. Includes control logic delay, skew, difference in delays of rising and falling edges, skew in clock path, PLL jitter, DLL jitter and DLL phase offset. Remaining budget is 315 ps for both setup and hold.

 

Blue: Remaining budget must capture all of the timing uncertainties associated with signal integrity, crosstalk, PCB and package impedance mismatch, termination mismatch and frequency dependent losses. These effects impact DQS as well as DQ signals. Therefore, accounting for all the losses from the remaining budget, Tsu is 195 ps, Thd is 285 ps.