Synopsys rolls next generation IC router

Synopsys already has a router in its IC Compiler product, but the company decided that customers needed something different for 45 nm and below. Synopsys this week (May 27) is rolling out ZRoute, a multi-threaded router that performs concurrent design for manufacturability (DFM) optimizations.

 

Compared to the existing IC Compiler router, ZRoute promises a 10X speed increase running on quad-core machines. It offers new routing technology, including a "dynamic maze grid" algorithm that allows off-grid routing. It can handle soft (recommended) design rules, redundant vias, and wire spreading during the routing. ZRoute is presented as a complete full-chip routing solution with global routing, track assignment, and detailed routing.

 

The router was built completely in house, according to Saleem Haider, senior director of marketing for physical design and DFM at Synopsys. "We built this from scratch, which we don't do that very often because we have a very rich technology base," he said. "With ZRoute, we made a completely clean start with a blank piece of paper and a separate team."

 

Haider noted, however, that ZRoute is fully integrated into IC Compiler, a toolset that includes physical synthesis, placement, routing, timing, signal integrity optimization, power reduction, design for test (DFT), and yield optimization. ZRoute will co-exist with the current IC Compiler router, he said, and customers can decide which one to use based on their needs.

 

"We're going to make the new router available to customers free of charge," he said. "The mainstream platform is four cores, and they'll be able to run with the same IC Compiler license they have. It may be different when we get to eight cores." Haider said Synopsys expects that most customers will continue with the current router until they finish their existing projects, and then pick up the new router when starting a new chip.

 

Compared to the existing router, Haider said, "we expect ZRoute to be better in every way. Once we deploy it we'll learn from experience, and there may be some areas where we'll discover we need to improve the new router, but the intention is for ZRoute to be strictly better than our current router." But Haider acknowledged that a complete replacement of the existing router is "far down the line." Some customers may stick with it, he said, if they want to continue using existing scripts, or if they're doing multiple revisions of one design.

 

Because the ZRoute development team started from scratch, they were able to bring in the "latest in routing research and routing algorithms," Haider said. One such feature is dynamic maze routing. This can be thought of as a grid that can be changed on the fly in specific instances. It allows the router to go off-grid to connect pins, while retaining the speed advantages of gridded routers.

 

Another new feature is "realistic connectivity." Haider explained that traditional routers model the center lines of wires, rather than the complete wire. Thus, for two lines to connect, the center lines have to connect. ZRoute's connectivity model uses a rectangle that represents the entire wire. As long as the rectangles touch, ZRoute knows there will be electrical connectivity.

 

ZRoute can efficiently handle advanced design rules for 45 nm and below, Haider said. In addition to hard (mandatory) rules imposed by the foundry, ZRoute can handle soft, or recommended rules that can improve yield. Users can specify additional soft rules.

 

ZRoute also has a built-in polygon manager. While it routes using wires and rectangles, it understands that design rule checks (DRCs) are aimed at polygons, and it can recognize polygons. Routers that can't recognize polygons, Haider noted, have to decompose everything into rectangles, adding more processing time.

 

 

 

Another ZRoute advantage compared to the existing IC Compiler router is concurrent DFM optimization. By considering soft rules, antennas, vias, and wire spreading during routing rather than as a post-processing step, ZRoute achieves better manufacturability, Haider said. Specifically, ZRoute claims 10 to 15 percent fewer vias overall, and 30 to 50 percent fewer single vias, than the current router. Reducing single vias results in a higher yield, he said.

 

Finally, all ZRoute routing steps – including global routing, track assignment, and detailed routing – are multi-threaded to take advantage of the multicore CPUs that are found in most workstations today. "New software has to be architected for that, and it is not a trivial thing to do. It is difficult to get it right so there's no impact on quality of results," Haider said.

 

Synopsys claims that ZRoute is already 3.5X faster than the current IC Compiler router when running in single-threaded mode. A quad-core CPU yields a 3X speedup over a single core, thus producing a net 10X speedup over the current IC Compiler router, which is not multi-threaded. Synopsys further claims that six cores will result in a 4X speedup over a single core, and eight cores will result in a 5X speedup. ZRoute hasn't yet been tried on more than eight cores, Haider said.

 

Multi-threading is transparent to the user and is easy to set up, Haider said. An additional benefit is that ZRoute's memory utilization is 20 to 25 percent lower than the current IC Compiler router.

 

ZRoute will be in limited production in June, with general availability scheduled for September. Announced customers include Matsushita and S3 Graphics. ZRoute will be shown at the June Design Automation Conference (DAC 2008).

 

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