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In My Opinion

'Off by Design' architectures curb energy waste

By Srikanth Jadcherla, Synopsys

03/25/08

Electronic devices are proliferating around the world in both developed and developing nations. The average household has more televisions, game consoles, media players, computers, and mobile phones than ever before. These devices are individually much more energy efficient than preceding generations. However, this is more than offset by the explosion in the number of devices per household and the number of households that can afford them.
 
This leads to a very big problem: devices need to get a lot more efficient or there will be a huge negative economic and environmental impact. The good news is that there is a significant and overlooked area for designers to focus on to curb energy waste. Power inefficiency occurs not just with active power consumption, but also idle power.
 
The average TV is active only about 20-25 percent of the time. Let us assume that, cumulatively, all the devices in a household consume about 10W in idle state, even though some studies estimate the real number is closer to 60W. Applying this assumption to just 25 percent of the 70 million households in the United States equates to a whopping 175 megawatts leaking all the time. In a single day, we waste about 15 million megawatts in the U.S.—just on idle devices. Then compute this across the world to see just how much energy is being wasted on idle devices.
 
Most devices have a clock and a remote control function, which is running and waiting for user input even when the device is functionally “off.” Consider a plasma TV. While the screen may have been powered off, electronics in the TV are still remembering channel history and screen settings, and are waiting for the next command input from the remote control. This can require as much as 5W to 8W on some models.
 
Another example is a home network router. Network traffic flow is characterized by short bursts of activity around long periods of idleness. Most router models consume around 10 to 50mA of current, or about 1 - 6W of power, just being idle. For many devices, like the router, a certain “state of readiness” is required of the device. Because this state is typically not efficiently implemented, there is significant power wastage.
 
A lot of effort goes into reducing active power because it makes systems bulkier, generates more heat, and limits performance. Idle power, on the other hand, is the slow killer. It is a fraction of dynamic power ─ sometimes just 1 to 2 percent of dynamic power ─ but is drawn all the time. In the span of a day, the total idle energy consumed may even exceed the active energy!
 

Idle efficiently

On a positive note, idle power is systemically easy to reduce. All of these systems are never used all of the time. The opportunity to reduce wasted energy is tremendous. Hence, we must design electronics to “idle efficiently.” This principle can be realized at the design level with an “Off by Design” architecture. Such a design must ideally satisfy two fundamental properties:
 
1.    Any part of the system must be powered up only when needed.
2.    Any part of the system that is not in use must be turned off.
 
Compliance with these two rules in the architecture implies that there is a “power manager” built into every IC and system. Such a power manager would have to be hardware and software savvy, since most modern systems and ICs are heavily coupled with software for their active/idle profile. 
 
The technically savvy user will point out a subtle corollary to the “Off by Design” concept. A system does not need to perform at the same level all the time. For example, on an HDTV, people often watch standard-definition television programs. Or a mobile phone may be used as just a phone most of the time, as opposed to serving as a camera or a video player. So, there are opportunities to run some components at significantly lower power. Such a technique can reduce the active power consumed.
 
Many IC designers in the mobile/consumer electronics world have already embarked on various design styles aimed at improving power efficiency—mostly aimed, however, at active mode heat reduction and increased battery life. The adoption of low power design techniques in the mobile/consumer world has led to the use of multi-voltage design, which in turn has caused a sea change in the way ICs are specified, implemented and verified. This can now be extended to “Off by Design” systems.
 
While “Off by Design” is conceptually ideal, practical implementations must consider many aspects. Partitioning an IC or a system into too many parts may actually be counter-productive. Some blocks have idle periods, but turning them on and off may be more wasteful than just leaving them on. Designing the power partitions of a system and choosing the low power mode entry/exit policy is one of the trickiest tasks that architects face.
 
Ultimately, however, idling efficiently is both the proper and the profitable thing to do. Despite some extra initial design costs, reducing power consumption promises to lower overall system costs in later versions. In addition, cost savings are per system and per usage period—not just for the design phase. It might very well be profitable to save the planet!
 
Srikanth Jadcherla is group director of R&D in the Verification Group at Synopsys. Jadcherla came to Synopsys as part of the ArchPro acquisition, where he was founder and CTO.
 
Related articles
 
Analyzing IC power at the electronic system level
Synopsys offers low-power IC design suite
Understanding RTL power reduction techniques
 

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