Open Verification Methodology offers interoperability

Engineers from around the world are beginning to access the Open Verification Methodology (OVM), the industry’s first open and interoperable methodology for SystemVerilog. Developed jointly by Mentor Graphics and Cadence Design Systems, the OVM combines technology from both companies to deliver on the two big promises of SystemVerilog – interoperability and advanced verification.

 

From the outset, the separate SystemVerilog approaches of Cadence and Mentor were on parallel tracks. Mentor’s Advanced Verification Methodology (AVM) was introduced in 2004 in open source, and came with supporting examples and documentation. Its adoption by many verification teams drove improvements that lead to AVM 3.0 in May of 2006. 

 

Similarly, the Cadence Universal Reuse Methodology (URM) was introduced in 2006 and was delivered with supporting examples and documentation. It was based on techniques in production use since 2002 with the e Reuse Methodology (eRM). Additionally, AVM and URM separately evolved similar class hierarchies, test phasing, transaction-level modeling (TLM) usage, and other capabilities.

 

Customer verification teams quickly recognized the similarities and asked Cadence and Mentor to work together. When the two engineering teams looked into building a joint methodology, they found it to be relatively simple not only to get the methodologies running on both simulators but also to combine them into one methodology that offered more capability than either.   The result is the OVM.

 

The OVM provides the building blocks needed by both new and expert SystemVerilog users to create modular, reusable verification environments. The OVM architecture lets new verification engineers get started quickly while also providing all the advanced capabilities that experts demand. The first step is to create an OVM component which automatically inherits the necessary infrastructure methods for communication and customization via the object-oriented structure of OVM.

 

These components are then connected to other parts of the verification environment through TLM. This is key to verification efficiency because the semantics of TLM allow components to be replaced without affecting the rest of the environment. Combined with flexible configuration, this capability makes it possible to create unique tests at run time by selecting from precompiled environments, allowing the environments to modify their own topology, and adding/modifying stimulus sequences on the fly to exercise different scenarios.

 

The stimulus sequences in the OVM enable engineers to build hierarchical sequences to handle a wide range of scenarios. In the simplest case, the engineer specifies the type of transaction to be generated along with any associated constraints, and the transaction is automatically randomized and sent to the driver. Engineers can layer these sequences hierarchically to model sophisticated protocols. These protocol sequences can then be coordinated with a hierarchical layer of virtual sequences. Superior productivity is achieved by decoupling these hierarchical sequences from the specific architecture of the testbench in which they are used.

 

 

 

At the system level, the use of consistent interfaces and communication semantics between components in OVM enables the creation of golden verification intellectual property (IP) for plug-and-play reuse (see Fig. 1).  For example, grouping all of the functionality necessary to verify a particular protocol or interface, including the protocol-level stimulus, signal-level behavior and checking and functional coverage in a single verification component, allows the component to be reused across multiple projects. Because these components have a consistent interface, they can be easily connected with other verification components, connected hierarchically, reconnected from design to design, or connected in a multi-language environment.

 

The newest development in the OVM world is its availability through OVMworld.org.  This website is jointly staffed by Cadence and Mentor and is open to everyone, including competitors. The site provides access to the OVM – including the source code, documentation, and examples – and more. Probably the most interesting part of the site is the very active forum where users have been discussing topics that dive into how the OVM runs in the different tool environments, how technical aspects of the OVM operate, possible next steps for the OVM, and more. With more than 1,100 engineers in the OVM community after one week and more joining every day, it is quickly turning into an OVM world.

 

A lunch panel at DVCon 2008, on Thursday, February 21, 2008, will include an open discussion and a firsthand look at OVM. It will be technical in nature and feature technologists from both Cadence and Mentor Graphics, who have contributed both technology and resources to develop the foundation of the methodology and class libraries.

 

 

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