Power is becoming a major design consideration for FPGAs. In this article we review why FPGA power consumption is increasing, and discuss various techniques that can be used to reduce it.Read more...
In My Opinion
Methodology standard will boost verification productivity
By Karen Bartleson
05/06/08
By defining a unified methodology for verification intellectual property (VIP) interoperability, Accellera's new VIP technical subcommittee can boost verification productivity, says Synopsys' Karen Bartleson. It can also head off a potential standards dispute between different SystemVerilog methodologies.Read more...
Contributed Article
How floorplanning guides synthesis and physical design
By Jack Erickson, Cadence Design...
05/06/08
Cadence Design Systems' Jack Erickson shows how to use floorplanning before synthesis with physical layout estimation (PLE), and before layout with silicon virtual prototyping (SVP). He discusses the floorplan information needed at each step.Read more...
News Analysis
Mentor taps NXP for design-for-test technology
By Richard Goering
05/07/08
Mentor Graphics has acquired rights to NXP Semiconductors' internal design for test (DFT) technology and tools, and has hired NXP DFT developers to staff a new R&D center in Germany. The deal gives Mentor new technology in automatic test pattern generation (ATPG) and yield learning.Read more...
News Analysis
New exhibitors bring fresh ideas to DAC
By Richard Goering
05/05/08
With some two dozen first-time exhibitors in 2008, the Design Automation Conference continues to provide a showcase for new solutions for system and chip design. We profile some of the EDA and silicon IP providers who are making their first appearance at the 45th annual DAC in June.Read more...
News Analysis
New standards effort targets verification IP interoperability
By Richard Goering
04/28/08
The Accellera standards organization has launched a verification IP (VIP) technical subcommittee that will seek to define a standard methodology to allow VIP interoperability and reuse, SCDsource has learned. The effort could head off a potential standards dispute involving Cadence Design Systems, Mentor Graphics and Synopsys.Read more...
SolutionSource™ Featured Company
Novas Software, Inc. is the leading provider of design comprehension solutions that enhance verification of complex ICs, embedded systems and SoCs. The Verdi™ Automated Debug and Siloti™ Visibility Enhancement products cut...Read more...
Startup Polyteda Software Corp. is developing physical verification software that will be able to handle complex ICs 10 or 15 years into the future, according to founder Vlad Marchuk, president and CEO. The company is making its first public appearance at the Design Automation Conference in June.Read more...
News Bytes
The Accellera standards organization has appointed Karen Pieper as its new Technical Committee chair, replacing Johny Srouji. Pieper, formerly the Technical Committee vice chair, is director of synthesis at startup Tabula.
U.K. engineering simulation provider Flomerics Group has rejected a cash buyout offer from Mentor Graphics, according to a Reuters report. Mentor holds a 26 percent share in Flomerics, which is reportedly in acquisition discussions with several other companies. Flomerics offers software for thermal analysis, engineering fluid dynamics, and heating/air conditioning simulation.
Synopsys has made an investment in formal verification provider Prover Technology, which provides signaling design automation solutions for transportation systems. The amount was not disclosed.
By defining a unified methodology for verification intellectual property (VIP) interoperability, Accellera's new VIP technical subcommittee can boost verification productivity, says Synopsys' Karen Bartleson. It can also head off a potential standards dispute between different SystemVerilog methodologies.
Cadence Design Systems' Jack Erickson shows how to use floorplanning before synthesis with physical layout estimation (PLE), and before layout with silicon virtual prototyping (SVP). He discusses the floorplan information needed at each step.
With some two dozen first-time exhibitors in 2008, the Design Automation Conference continues to provide a showcase for new solutions for system and chip design. We profile some of the EDA and silicon IP providers who are making their first appearance at the 45th annual DAC in June.
Novas Software, Inc. is the leading provider of design comprehension solutions that enhance verification of complex ICs, embedded systems and SoCs. The Verdi™ Automated Debug and Siloti™ Visibility Enhancement products cut...
Startup Polyteda Software Corp. is developing physical verification software that will be able to handle complex ICs 10 or 15 years into the future, according to founder Vlad Marchuk, president and CEO. The company is making its first public appearance at the Design Automation Conference in June.